In PCIe (Peripheral Component Interface express) and other high speed SerDes (Serializer-Deserializer) links, the receiver eye opening tolerance range is a key analog design feature. In general, external equipment is needed to generate a constrained signaling to a receiver and to evaluate the receiver data receiving performance. For example, a tester applies a test pattern (bit stream) to a device under test (a receiver), which sends the test pattern back to the tester for determining the bit error rate, i.e., the performance of the device under test (the receiver).
Generally, a bit error rate (BER) of an interconnect or link is a key indicator of a communication system. To determine the BER of a link or the performance of a device under test (DUT), an eye mask measurement is generally performed. The eye mask measurement is performed at an input of the device under test. However, an eye mask measurement at a close proximity of an DUT input with external test equipment is difficult and requires multiple firmware interactions between the DUT and the external test equipment. In addition, external test equipment is generally expensive and has limited use.
The present invention provides technical solutions to overcome the complex and inefficient firmware interactions.